Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization
US6505306B1 · kind B1 · utility
17Cited by
9References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.