Semiconductor device, tab tape for semiconductor device, method of manufacturing the tab tape and method of manufacturing the semiconductor device
US6506627B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure of a semiconductor device of a chip scale package structure is provided. In the semiconductor device, the limitation to size reduction due to the bonding tool is small and the bonding pitch of the semiconductor chip can be reduced to 100 &mgr;m or less, and the chip shrink technique of a technique for lowering the cost can be employed and in connection with this compatibility among packages can be kept.The semiconductor device includes a semiconductor chip; a TAB tape being directly laminated onto a circuit formed surface of the semiconductor chip or being laminated through a stress moderating elastomer onto the circuit formed surface of the semiconductor chip, the TAB tape having leads made of a metallic film formed on an insulator tape having flexibility; and an externally connecting member formed in an end of the lead of the TAB tape, wherein the TAB tape has holes in the insulator tape, each of the holes corresponding to a bonding pad formed on a circuit formed surface of the semiconductor chip at a position corresponding to a position of the bonding pad; the lead being formed so as to bridge across the hole; and the lead formed above the hole being joined to the bo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.