Removable spacer technique

US6506642B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Scott Luning · San Francisco, US
• Jon D. Cheek · Wallkill, US
• Daniel Kadosh · Austin, US
• James F. Buller · Austin, US
• David E. Brown · Pleasant Valley, US

Key dates

• Filing date: Dec 19, 2001
• Grant date: Jan 14, 2003
• Expiry date: Dec 19, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.