Stepped collector implant and method for fabrication
US6506656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Mar 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/60
Abstract
The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.