Multiple loadlock system
US6506693B2 · kind B2 · utility
5Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2002 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Mar 6, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/908
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.