Cu-balanced substrate
US6507100B1 · kind B1 · utility
23Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate is formed with electrically non-functional areas of Cu on the upper surface and/or lower surface for improved strength and rigidity and reduced warpage and bending. Embodiments of the present invention include substrates containing electrically non-functional grid-like Cu areas on the upper and lower surface such that the ratio of the total Cu area on one surface is about 55% to about 100% of the total Cu area on the other surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.