Electronic package and method of forming
US6507116B1 · kind B1 · utility
73Cited by
14References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package and method of making same in which a thermally conductive member is in thermally conductive communication with a semiconductor chip encapsulated within a dielectric material that surrounds portions of a thermally conductive member, semiconductor chip, and a predefined portion of a circuitized substrate. The present invention's thermally conductive member includes two portions of different bending stiffness to assure reduced interfacial stresses between the semiconductor chip and the circuitized substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.