Process for protecting array top oxide

US6509226B1 · kind B1 · utility

Assignees

• International Business Machines Corporation · US
• Infineon Technologies AG · DE

Inventors

• Venkatachalam C. Jaiprakash · Sunnyvale, US
• Jack A. Mandelman · Stormville, US
• Ramachandra Divakaruni · Ossining, US
• Rajeev Malik · Pleasantville, US
• Mihel Seitz · Wappingers Falls, US

Key dates

• Filing date: Sep 27, 2000
• Grant date: Jan 21, 2003
• Expiry date: Sep 27, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/038

Abstract

Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysil…