Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device
US6509232B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/44
Abstract
STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.