Method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate
US6509274B1 · kind B1 · utility
7Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2000 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Aug 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76882
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate that can compensate for some misalignment between the filled vias and the lines. By alternately depositing liner-barrier layers and aluminum layers on the substrate, different etch chemistries can be used that can anisotropically etch an aluminum layer used to form the lines without etching voids in the aluminum-filled vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.