Variable read/write margin high-performance soft-error tolerant SRAM bit cell
US6510076B1 · kind B1 · utility
36Cited by
7References
19Claims
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Key dates
| Filing date | Feb 12, 2002 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Feb 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single event upset (SEU) tolerant SRAM bit cell for six-transistor (6T), eight-transistor (8T), or multi-port RAM cell configurations fabricated in accordance with 0.18 &mgr;m or smaller CMOS processes. SEU tolerance is achieved without significantly increasing the cell's read and write cycle time and negligible impact on cell stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.