Method for generating memory addresses for accessing memory-cell arrays in memory devices
US6510102B2 · kind B2 · utility
1Cited by
30References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate memory addresses for functional testing of the memory cells within the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.