High mobility FETS using A1203 as a gate oxide
US6511876B2 · kind B2 · utility
46Cited by
7References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMOS processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.