Erase method for dual bit virtual ground flash
US6512701B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Jun 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.