Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6514671B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Sep 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.