Method for fabricating a dual metal gate for a semiconductor device
US6514827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first region. The first region is either the PMOS or NMOS region, and the remaining region becomes a second region. A dummy gate is formed in the second region. A spacer and a source/drain region are formed for each of the first and dummy gates. The dummy gate, however, is removed to expose a portion of the substrate in the second region. A second gate constructed of a second gate insulating layer and a second metal layer is then formed on the exposed portion of the substrate in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.