Multi-layer lead frame for a semiconductor device
US6515353B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Aug 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19103
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.