Passivation layer for packaged integrated circuits
US6515355B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1998 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Passivating layers methods for forming the same are provided for packaged integrated circuit devices. In particular, an integrated circuit die is mounted in a plastic leaded chip carrier, and a photosensitive material is then deposited over the surfaces to be passivated. Portions of the photosensitive material are then exposed to UV light, resulting in a crosslinked siloxane network. In this way, a low-temperature photodefinable passivation layer is provided for the package, with characteristics similar to conventional oxides. Advantageously, the photosensitive material can be patterned during the UV exposure, and unexposed portions selectively removed to leave the passivation layer only over desired portions of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.