Semiconductor buffer circuit with a transition delay circuit
US6515529B2 · kind B2 · utility
1Cited by
5References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Aug 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.