Memory module with parallel stub traces
US6515555B2 · kind B2 · utility
5Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Dec 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board is described. That printed circuit board includes a capacitive load that is coupled to a signal trace. The signal trace has a first section and a second section. The first section is positioned between the capacitive load and the second section. The second section has a first width, and the first section includes first and second lines that each have a width that is smaller than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.