Junction-isolated depletion mode ferroelectric memory
US6515889B1 · kind B1 · utility
13Cited by
26References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Aug 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.