Balanced sense amplifier control for open digit line architecture memory devices
US6515925B2 · kind B2 · utility
12Cited by
4References
73Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Mar 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.