Process of forming a semiconductor device and a semiconductor device
US6518070B1 · kind B1 · utility
9Cited by
36References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | May 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/891
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming a capacitor with a high-k dielectric or ferroelectric layer within a semiconductor device is used to reduce the likelihood of oxidation or materials interactions between that layer and an underlying layer. A first electrode layer includes atoms that form along grain boundaries within the first electrode layer to reduce the oxidation of a conductive plug or undesired materials interactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.