Chun-Li Liu
56Patents
9h-index
56Co-inventors
81Inventor score
Filing activity: May 17, 2000 → Sep 12, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6831350B1 | Semiconductor structure with different lattice constant materials and method for forming the same | Electricity | 78 | Expired |
| US7238580B2 | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration | Electricity | 43 | Expired |
| US7221006B2 | GeSOI transistor with low junction current and low junction capacitance and method for making the same | Electricity | 32 | Expired |
| US6717226B2 | Transistor with layered high-K gate dielectric and method therefor | Electricity | 30 | Expired |
| US7932189B2 | Process of forming an electronic device including a layer of discontinuous storage elements | Emerging Cross-Sectional Technologies | 14 | Active |
| US7029980B2 | Method of manufacturing SOI template layer | Emerging Cross-Sectional Technologies | 13 | Expired |
| US9673311B1 | Electronic device including a multiple channel HEMT | Electricity | 13 | Active |
| US7166897B2 | Method and apparatus for performance enhancement in an asymmetrical semiconductor device | Electricity | 10 | Expired |
| US7544576B2 | Diffusion barrier for nickel silicides in a semiconductor fabrication process | Electricity | 10 | Active |
| US6518070B1 | Process of forming a semiconductor device and a semiconductor device | Electricity | 9 | Expired |
| US9257513B1 | Semiconductor component and method | Electricity | 7 | Active |
| US9799646B2 | Cascode configured semiconductor component | Electricity | 5 | Active |
| US9748224B2 | Heterojunction semiconductor device having integrated clamping device | Electricity | 5 | Active |
| US9620598B2 | Electronic device including a channel layer including gallium nitride | Electricity | 4 | Active |
| US7935620B2 | Method for forming semiconductor devices with low leakage Schottky contacts | Electricity | 4 | Active |
| US9842920B1 | Gallium nitride semiconductor device with isolated fingers | Electricity | 4 | Active |
| US7700438B2 | MOS device with nano-crystal gate structure | Electricity | 3 | Active |
| US7241647B2 | Graded semiconductor layer | Electricity | 3 | Expired |
| US9735095B2 | Semiconductor component and method of manufacture | Electricity | 2 | Active |
| US7928502B2 | Transistor devices with nano-crystal gate structures | Electricity | 2 | Active |
| US7056778B2 | Semiconductor layer formation | Emerging Cross-Sectional Technologies | 2 | Expired |
| US9818677B2 | Semiconductor component having group III nitride semiconductor device mounted on substrate and interconnected to lead frame | Electricity | 2 | Active |
| US9214423B2 | Method of forming a HEMT semiconductor device and structure therefor | Electricity | 1 | Active |
| US8592878B2 | Semiconductor devices with low leakage Schottky contacts | Electricity | 1 | Active |
| US10199373B2 | Method of forming a heterojunction semiconductor device having integrated clamping device | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.