Semiconductor device and a method therefor
US6518106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | May 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.