Method for avoiding fluorine contamination of copper interconnects
US6518173B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Corrosion and degradation of tantalum-based adhesion/barrier layers used in multi-level semiconductor devices employing copper-based interconnect metallization systems are avoided or minimized. In embodiments of the present invention, deleterious fluorine-containing contaminants formed on underlying copper-based metal features as a result of etching through-holes in silicon-based interlevel dielectric material layers for via holes is prevented by the use of fluorine-free etching processes. Other embodiments of the present invention include performing a two-step etching sequence comprising a first, fluorine-containing process and a second, fluorine-free process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.