Semiconductor devices
US6518594B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1999 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Nov 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/12
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.