Deep slit isolation with controlled void
US6518641B2 · kind B2 · utility
24Cited by
35References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | May 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/764
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.