Method for making a semiconductor chip package
US6521480B1 · kind B1 · utility
37Cited by
31References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Aug 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor chip package. At least one compliant pad is provided on a surface of a substrate and a chip unit is attached to the at least one compliant pad. The at least one compliant pad has a first coefficient of thermal expansion (“CTE”). An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed around the at least one compliant pad to form a composite layer between the chip unit and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.