Method for manufacturing wafer level chip size package
US6521485B2 · kind B2 · utility
28Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Mar 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.