Ball grid array chip packages having improved testing and stacking characteristics
US6522018B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2000 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low profile BGA or FBGA semiconductor package is needed. The present invention provides a semiconductor package which is capable of being burned in and tested in a more efficient and cost effective manner than prior known BGA or FBGA semiconductor packages. A high density, low profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.Exemplary BGA or FBGA semiconductor packages of the present invention generally comprise a substrate having a semiconductor device attached to a selected surface thereof. The semiconductor device has a plurality of bond pads respectively wire bonded to a plurality of bond pads located on the substrate. The substrate is preferably provided with a plurality of circuit traces leading from the substrate bond pads to a plurality of connective elements, such as solder ball contact pads and associated solder balls, arranged in a preselected ball grid array pattern and to a plurality of test pads arranged in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.