Wuu Yean Tay
29Patents
10h-index
18Co-inventors
68Inventor score
Filing activity: May 16, 2000 → Jun 19, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6522018B1 | Ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 184 | Expired |
| US6420789B1 | Ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 47 | Expired |
| US7754531B2 | Method for packaging microelectronic devices | Emerging Cross-Sectional Technologies | 39 | Active |
| US6693363B2 | Ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 37 | Expired |
| US6448664B1 | Ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 27 | Expired |
| US6787923B2 | Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks | Electricity | 16 | Expired |
| US7915718B2 | Apparatus for flip-chip packaging providing testing capability | Electricity | 15 | Expired |
| US6600335B2 | Method for ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7030640B2 | Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress testing of integrated circuits and method thereof | Physics | 12 | Expired |
| US7071012B2 | Methods relating to the reconstruction of semiconductor wafers for wafer-level processing | Electricity | 10 | Expired |
| US6740984B2 | Ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 8 | Expired |
| US6674175B2 | Ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 7 | Expired |
| US7061124B2 | Solder masks including dams for at least partially surrounding terminals of a carrier substrate and recessed areas positioned adjacent to the dams, and carrier substrates including such solder masks | Electricity | 7 | Expired |
| US6522019B2 | Ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 7 | Expired |
| US6856155B2 | Methods and apparatus for testing and burn-in of semiconductor devices | Physics | 6 | Expired |
| US6847220B2 | Method for ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6740983B2 | Method for ball grind array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 5 | Expired |
| US7368391B2 | Methods for designing carrier substrates with raised terminals | Emerging Cross-Sectional Technologies | 5 | Expired |
| US7018871B2 | Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks, and methods | Electricity | 4 | Expired |
| US7190074B2 | Reconstructed semiconductor wafers including alignment droplets contacting alignment vias | Electricity | 4 | Expired |
| US7285971B2 | Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress testing of integrated circuits and method thereof | Physics | 3 | Expired |
| US8525320B2 | Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods | Electricity | 3 | Active |
| US7116122B2 | Method for ball grid array chip packages having improved testing and stacking characteristics | Emerging Cross-Sectional Technologies | 3 | Expired |
| US7820459B2 | Methods relating to the reconstruction of semiconductor wafers for wafer level processing including forming of alignment protrusion and removal of alignment material | Electricity | 1 | Active |
| US7425462B2 | Methods relating to the reconstruction of semiconductor wafers for wafer-level processing | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.