Shared bus non-sequential data ordering method and apparatus
US6523080B1 · kind B1 · utility
1Cited by
13References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1998 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jan 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.