Method for adding decoupling capacitance during integrated circuit design
US6523159B2 · kind B2 · utility
18Cited by
6References
52Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.