Junctionless antifuses and systems containing junctionless antifuses
US6525399B2 · kind B2 · utility
17Cited by
23References
58Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Nov 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.