Wafer-level burn-in and test
US6525555B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.