Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6525953B1 · kind B1 · utility
324Cited by
118References
49Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Aug 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.