Automatic bitline-latch loading for flash prom test
US6525973B1 · kind B1 · utility
6Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Dec 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A one-shot system for loading a bitline shift register with a typical test pattern is described. Each bitline latch within the bitline shift register is augmented with a one-shot circuit that may pull-up or pull-down the value stored in the bitline latch. The choice of a particular memory test pattern dictates the control of the one-shot circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.