Method for efficient manufacturing of integrated circuits
US6526547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Aug 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention pertains to a method for the systematic development of integrated chip technology. The method may include obtaining empirical data of parameters for an existing integrated circuit manufacturing process and extrapolating the known data to a new technology to assess potential yields of the new technology from the known process. Further, process variables of the new process may be adjusted based upon the empirical data in order to optimize the yields of the new technology. A logic based computing system such as a fuzzy logic or neural-network system may be utilized. The computing system may also be utilized to improve the yields of an existing manufacturing process by adjust process variables within downstream process tools based upon data collected in upstream process for a particular semiconductor substrate or lot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.