Process for fabricating a non-volatile memory device
US6528390B2 · kind B2 · utility
33Cited by
7References
16Claims
0Family size
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Key dates
| Filing date | Mar 2, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Mar 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.