Process of fabricating an integrated circuit
US6528419B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 21, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process produces at a predetermined metallization level at least one metal track (7) within an intertrack dielectric material (1). The process includes the steps of etching the intertrack dielectric material (1) so as to form a cavity (4) at the position of the track, depositing a conducting barrier layer (5) in the cavity (4), filling the cavity (4) with copper, and depositing a silicon nitride layer (8) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi2 (60) during the diffusion of the silicon from the silicon nitride layer (8).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.