Integrated circuit structure having a charge injection barrier
US6528829B1 · kind B1 · utility
0Cited by
25References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/82
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.