Conformal atomic liner layer in an integrated circuit interconnect
US6528884B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method, and an integrated circuit resulting therefrom has a substrate with a semiconductor device thereon. A channel dielectric layer is deposited over the device and has an opening provided therein. A reducing process is performed in order to reduce the oxidation on the conductor and a conformal atomic liner is deposited in an atomic layer thickness to line the opening in the channel dielectric layer. A barrier layer is deposited over the conformal atomic liner and a seed layer is deposited over the barrier layer. A conductor core layer is deposited on the seed layer, filling the opening over the barrier layer and connecting to the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.