Patent · US Expired

Configuration for testing a plurality of memory chips on a wafer

US6529028B1 · kind B1 · utility

0Cited by

6References

4Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dieter Harle · Hersbruck, DE
Patrick Heyne · Hersbruck, DE
Martin Buck · Hersbruck, DE

Key dates

Filing date	Apr 30, 1999
Grant date	Mar 4, 2003
Priority date	—
Expiry date	Apr 30, 2019

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/56
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A configuration for testing a plurality of memory chips on a wafer, in which needles are used to supply the memory chips with supply voltages, an initialization signal, a read signal, a clock signal as well as address, data and control signals. The address, data and control signals are in this case produced by a logic device disposed in an edge area of the memory chip and are supplied directly to the memory chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.