Integrated series schottky and FET to allow negative drain voltage
US6529034B1 · kind B1 · utility
16Cited by
2References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 7, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Nov 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/105
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.