Device modeling and characterization structure with multiplexed pads
US6530068B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Aug 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiplexed transistor characterization and modeling structure for testing a plurality of transistors, The characterization and modeling structure comprises a common substrate pad, a common source pad, a plurality of drain pads, and a plurality of gate pads. The characterization and modeling structure further comprises a plurality of individual transistors. Each individual transistor comprises a substrate connected to the common substrate pad, a source connected to the common source pad, a drain connected to a single drain pad, and a gate connected to a single gate pad, wherein each individual transistor is connected to a different drain pad and gate pad combination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.