Method for fabricating a memory cell array

US6531359B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Georg Tempel · Zorneding, DE
• Christoph Kutter · Munich, DE

Key dates

• Filing date: Jun 19, 2000
• Grant date: Mar 11, 2003
• Expiry date: Jul 17, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/00

Abstract

A method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, includes burying insulation zones on a silicon substrate in accordance with an STI (Shallow Trench Isolation) technique, forming word lines on the insulation zones, covering the word lines with a hard mask and side wall oxides and CVD depositing an oxide or nitride laterally onto the hard mask and onto the side wall oxides to define a spacer. Spacer channels are etched into the insulation zones between adjoining word lines. An SAS (Self Aligned Source) resist mask is applied to mask each two adjacent coated word lines on mutually facing sections, including the spacer channel located between these word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked on mutually facing sections. The SAS resist mask is exposed. Those regions of the insulation zones which are not covered by the SAS perforated mask are anisotropic etched, with a bottom of uncovered spacer channels being lowered down at least to a surface of the uncovered silicon substrate. The SAS perforated mask is removed to uncover a resultant structure.