Event based semiconductor test system
US6532561B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1999 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Sep 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.