Method of fabricating memory cell

US6534359B2 · kind B2 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Kuen-Chy Heo · Chiayi, TW
• Jeng-Ping Lin · Taoyuan, TW

Key dates

• Filing date: May 15, 2001
• Grant date: Mar 18, 2003
• Expiry date: May 15, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

A method of fabricating a vertical transistor of a memory cell is disclosed. Accordinng to this method, a semiconductor substrate is first provided. A pad layer is formed on the surface of the substrate. A deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is deposited to form a buried strap and an opening. A first insulating layer and a second masking layer are formed and fill the opening. The pad layer, the substrate, the second masking layer, the first insulating layer, the collar oxide layer and the first conductive layer are patterned. A second insulating layer is deposited and forms a Shallow Trench Isolation. A portion of the second masking layer is removed. The pad layer is removed to expose the substrate. A well is formed in the exposed substrate after forming a third insulating layer. The third insulating layer and the first insulating layer are then removed. The second masking layer is removed. A fourth insulating layer is deposited to form the gate oxide. Sequentia…