Single damascene method for RF IC passive component integration in copper interconnect process
US6534374B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of integrated circuit component integration in copper interconnects, including the following steps of the first embodiment. A wafer is provided having an exposed top-most planar copper interconnect. The wafer being divided into one or more areas selected from the group consisting of: a spiral inductor area having an exposed planar copper interconnect bottom half of a stacked spiral inductor; a MIM capacitor area having an exposed planar copper interconnect bottom plate and an exposed planar copper interconnect contact point of a MIM capacitor; and a precision resistor area having a two exposed planar copper interconnect routing points of a precision resistor. A spiral inductor is formed within the spiral inductor area; a MIM capacitor is formed within the MIM capacitor area; and a precision resistor is formed within the precision resistor area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.